The demand for semiconductor devices having a Cu line has been increasing due to the low resistance of the Cu line. As a result, various types of semiconductor devices having a Cu line have been recently developed. Cu lines are usually deposited on a copper seed layer (e.g., a Ta(Tantalum)/TaN(Tantalum nitride) double layer), which also serves as a Cu diffusion barrier that prevents copper in the Cu line from being diffused, by a dual damascene process.
However, the contacts of semiconductor devices are usually implemented using a tungsten plug (W-plug) fabricated using a single damascene process instead of a dual damascene process, which is usually used to form the Cu line and a via hole.
To form the tungsten plug, both a tungsten CMP (chemical mechanical polishing) process and a touch-up process, which is a follow-up process to the tungsten CMP process, are required. However, in the course of the touch-up process, wafer surfaces are often scratched microscopically and macroscopically and insulating layers are often ripped out by oxide particles.
Moreover, the Ta/TaN double layer, which serves as the Cu diffusion barrier at an interface between the tungsten plug and the Cu line, may collapse in the course of a Cu CMP process due to a void (i.e., a vacant region in the tungsten plug) generated during a tungsten CVD (chemical vapor deposition) process.
FIGS. 1A to 1F show a conventional method for forming a contact using the tungsten plug and the single damascene process, sequentially. As shown in FIG. 1A, a PMD (pre-metal dielectric) layer 102 is photo-lithographically etched to form a contact hole 104. Thereafter, as shown in FIG. 1B, a tungsten diffusion barrier 106 (e.g., a Ti(Titanium)/TiN(Titanium nitride) double layer) is deposited on the PMD layer 102 and sidewalls and an undersurface of the contact hole 104, and then a tungsten layer 108 is deposited on the tungsten diffusion barrier 106 by the tungsten CVD process.
In the course of the CVD process, the tungsten layer 108 begins to grow from the sidewalls of the contact hole 104 so that the void can be produced at the center of the contact hole 104.
Then, as shown in FIG. 1C, the tungsten layer 108 and the tungsten diffusion barrier 106 above the PMD layer 102 are removed by the tungsten CMP process and the touch-up process to form a tungsten plug 109, which has substantially the same height as that of the PMD layer 102. The tungsten layer 108 is polished by the tungsten CMP process and, tungsten residue, which was not completely removed during the tungsten CMP process, is removed by the touch-up process (e.g., an oxide CMP process). Thereafter, as shown in FIG. 1D, an additional PMD layer 103 is deposited on both sides of the PMD layer 102 to form a trench 110 having a width greater than that of the tungsten plug 109.
Then, as shown in FIG. 1E, a Cu diffusion barrier 11 (e.g., a Ta/TaN double layer) is deposited on the additional PMD layer 103 and sidewalls and an undersurface of the trench 110, and then copper 112 is deposited on the Cu diffusion barrier 111. Then, as shown in FIG. 1F, the copper 112 over the trench 110 is removed by a Cu CMP process to form a Cu line 113.
The above-described conventional method must utilize the touch-up process because the additional PMD layer 103 should be deposited on a clean surface of the PMD layer 102 to reduce a leakage current that may be caused by tungsten residue remaining at an interface of the PMD layers 102 and 103. However, as noted above, the wafer surfaces may be scratched microscopically and macroscopically and the insulating layers may be ripped out during the touch-up process.
Further, with the above-described conventional method, the void can be exposed after the tungsten CMP process or the touch-up process so that the Cu diffusion barrier 111 cannot be deposited over the void. Thus, in the course of the Cu CMP process, the copper in the Cu line 113 can be diffused to the silicon substrate 100 via the tungsten diffusion barrier 106 which cannot serve as the Cu diffusion barrier. Even if the void is not exposed after the tungsten CMP process or the touch-up process, the Cu diffusion barrier 111 may collapse to thereby expose the void by a pressure exerted during the Cu CMP process, so that the copper in the Cu line 113 can be diffused to the silicon substrate 100 via the tungsten diffusion barrier 106 in the same way.
Still further, with the above-described conventional method, the contact resistance between the tungsten plug 109 and the Cu line 113 is high because the width of the contact region therebetween is narrow.